This invention relates, in general, to a method for making semiconductor integrated circuits, and more particularly, to a process for making a high voltage bipolar transistor integrated circuit.
The present technique for making high voltage (between 20 volts and 150 volts) bipolar transistors uses a low doped, thick silicon epitaxial layer. This thick silicon epitaxial layer causes some undesirable limitations. As an example, in order to create an isolation region for a transistor, long drive in times, at high temperatures, are necessary in order to drive in the dopants to create the isolation area. As a consequence, the lateral diffusion of the isolation area increases the minimum transistor size. Also such thermal cycles enhance the up diffusion of the buried layer thus reducing the active silicon layer under the bipolar transistor base. In this type of process the epitaxial layer must be thick in order to ensure an effective active layer underneath the base area. An example of such a device can be found in U.S. Pat. No. 3,982,974, which issued to Edel et al on Sept. 28, 1976.
The low dopant concentration necessary for the higher voltage bipolar transistors allows an increase in the expansion of the depletion spread between the base area and the isolation area. This results in requiring the spaces between these areas to be increased. Also the devices are extremely sensitive to the surface effects at the interface between the silicon epitaxial layer and a covering oxide layer. Often guard rings are required in order to eliminate the parasitic effects occurring near the surface. Therefore, it would be desirable to eliminate some of the negative effects of the thick epitaxial layer in order to increase the circuit density or the number of circuits per unit of silicon area.
Accordingly, it is an object of the present invention to provide an improved bipolar integrated circuit.
Another object of the present invention is to provide a high voltage bipolar integrated circuit having a reduced size.
Yet another object of the present invention is to provide a three layer epitaxial process with self-aligned isolation for highly dense and low cost high voltage bipolar integrated circuits.
Yet a further object of the present invention is to provide a bipolar integrated circuit capable of handling a higher voltage yet consuming less silicon area.